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NEM Relays

The Stanford NEMS group is involved in the design of nanoelectromechanical (NEM) switches, and their integration into electronic devices. As CMOS transistors become smaller, they approach a physical limit of energy efficiency which leads to high leakage currents in the off-state. In contrast, NEM switches are not subject to the same limit as transistors because they physically move to make and break contacts, thus eliminating leakage currents when the device is turned off. Our group's work focuses on improving relay reliability, reducing operating voltages, and developing fabrication processes and designs that are compatible with CMOS devices.

The NEM relay research is performed by a multi-disciplinary group with many collaborations across many schools. We focus on not only the electrical and mechanical design, but also material considerations and packaging. Our group relies on a lateral switching design which allows for smaller overall footprint and energy reversible operation [Roozbeh Parsa Thesis (2008)]. We have introduced a decoupled design that separates the mechanical and electrical design constraints using simple geometry as described in [Parsa et al., MEMS 2011] and [Harrison et al., Transducers 2013]. We have also investigated the material design of the contact by depositing a thin film on the sidewalls of our devices. Currently, we rely on an ALD Titanium Nitride film to improve our contact conductivity and wear properties [Shavezipur et al., Nanotech 2013]. We have improved contact mechanics for ultra-small relays by creating a thin, conformal film at the contact area which can increase the real area of contact in asperity-dominated interfaces [Shavezipur et al., MEMS 2013]. We have furthered the understanding of thermal behavior at the contact by developing new analytical methods based on thin film heating at the contact [Harrison et al., iTHERM 2014].

Through collaborations, we have applied our NEM relay designs to new domains. We have worked with the Stanford Microstructures and Sensors Lab to develop charge biased resonators using relays to isolate the charged resonator inside of a hermetically sealed cavity from the probe pads, thus reducing charge leakage [Ng et al, MEMS 2014]. We have also collaborated with IME in Singapore to develop a process for laterally actuated NEM relays in a sealed environment.

Our current work involves the integration of NEM relays with CMOS devices for energy efficient hybrid systems. Our target application is NEM relay routing matrices for Field Programmable Gate Arrays (FPGA). It has been shown that the leakage power loss and footprint of FPGAs can be dramatically reduced by replacing SRAM cells with NEM relays for routing [Chen et al., DATE 2012]. We are currently collaborating with University of California Berkeley to develop integrated CMOS-NEM Relay fabricated devices. The main thrust of this work involves NEM relay scaling, material selection and process engineering for integration.